1. Technical Field
The present disclosure relates to communication techniques.
The disclosure has been developed with particular attention paid to its possible use in the so-called Network-in-Package (NiP) architectures, such as the ones used for communication between different circuits integrated within a System-in-Package (SiP) that require a high level of performance.
2. Description of the Related Art
Systems-in-Package (SiPs) are heterogeneous electronic systems that comprise a plurality of integrated circuits. For instance, said integrated circuits are frequently mounted directly as dice in a common package and communicate with one another via a network for communication within the package, referred to as Network-in-Package (NiP).
For instance, such SiPs are particularly useful for interfacing integrated circuits that have been produced with different manufacturing processes.
For instance, the improvement of the processes for manufacturing integrated circuits enables reduction of the so-called “feature size”, i.e., the size of the elements within the integrated circuit, and, from the reduction in the feature size, there also follows a respective reduction in the size of the entire integrated circuit. For instance, the size of a digital integrated circuit decreases typically by 55% when the same circuit is implemented with a 65-nm technology instead of a 90-nm technology.
However, said improvement does not extend directly to the analog or input/output (I/O) cells, which leads to severe limitations during design of complex systems within an integrated circuit such as Systems-on-Chip (SoCs).
For instance, in some cases, the core of the integrated circuit can be small, but the size of the integrated circuit must be increased on account of the number and/or size of the pads of the integrated circuit, this being known as “pad-limited design.”
Furthermore, when a technology with small feature size is used, for example a sub32-nm technology, a high speed of the I/O logic can, in some cases, only be achieved with a low supply voltage. For instance, a memory of the Double-Data-Rate version 3 (DDR3) type can work at an operating frequency of 800 MHz and a supply voltage of 1.5 V.
However, complex circuits can also comprise communication interfaces with higher voltages, for example a communication interface of the “High-Definition Multimedia Interface” (HDMI) type, of the “Serial Advanced Technology Attachment” (SATA) type, or of the “Universal Serial Bus” version 3 (USB3) type. For instance, in one case, the communication interface of the DDR3 memory forms a gate oxide with a thickness of 30 Å, whereas the HDMI communication interface would form a thickness of 50 Å. However, this case cannot be obtained with a single manufacturing process.
Instead, said system can be obtained via a System-in-Package by separating the subcircuits of the traditional SoC into a plurality of dice (i.e., a plurality of integrated circuits) to form a System-in-Package. For instance, said SiP could consist of a first die (i.e., a first integrated circuit) obtained with a 32-nm technology that comprises the digital processing circuits, for example a high-speed processor, a DDR3 control unit, and other Intellectual-Property (IP) cores. Said first die can be connected to a second die (i.e., a second integrated circuit) obtained with a 55-nm technology that comprises analog circuits and/or various communication interfaces.
However, in this architecture, the communication between the aforesaid dice is exchanged at a package level.